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features real time clock/calendar functions includes: sec, minutes, hours, day, date, month, and year in bcd format clock operating voltage: 2.0v~5.5v supply voltage v dd =2.7v~5.5v automatic leap year correction, valid until year 2099 automatic supply switch over integrated oscillator load capacitors - cl=12.5pf clock compensation programmable alarm and interrupt function 15 selectable frequency outputs 4 bytes eeprom for user serial commutation via i 2 c or 3-wire interface 8-pin dip, sop and msop package for i 2 c interface 10-pin msop package for 3-wire interface applications utility meters consumer electronics portable equipment wireless equipment pos equipment computer products other industrial/medical/automotive applications general description the HT1382 is a low power real time clock device with two serial interface: i 2 c or 3-wire. the interface mode is selected by the chosen chip version. the device provides both clock and calendar information in bcd format and also includes alarm functions. the calendar is accurate until the year 2099 and includes automatic leap year correction. an external 32768hz crystal is used as the device oscillator for device timing for which is provided an integrated crystal load capacitance of 12.5pf. the device includes a crystal oscillator temperature compensation function and internal power control circuitry detects power failures and automatically switches to the battery supply when a power failure occurs. HT1382 i 2 c/3-wire real time clock rev. 1.20 1 march 8, 2011
block diagram note: ifs pin is used for selecting i 2 c interface or 3-wire interface. i 2 c interface is selected when ifs is unconnected. 3-wire interface is selected when ifs is connected to vss. pin assignment rev. 1.20 2 march 8, 2011 HT1382 i 2 c/3-wire real time clock

crystal oscillator x1 x2 /fout irq control & status register alarm register rtc register oscillator compensation scl/sclk i 2 cor3-wire interface divider circuit sda/i/o ifs vss dt & user eeprom ce vbat vdd internal power supply v comp switch
pad assignment chip size: 1245 1520 ( m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. pad coordinates unit: m pad no. x y pad no. x y 1 520.005 161.460 6 520.005 646.610 2 520.005 256.460 7 521.000 625.000 3 520.005 360.130 8 521.000 530.000 4 520.005 455.130 9 521.000 425.300 5 520.005 550.130 10 516.450 288.400 pad description pad no. pad name i/o description 1 x1 i 32768hz crystal input pin 2 x2 o 32768hz crystal output pin 3 vbat battery power supply 4 vss negative power supply, ground 5 ifs i interface selection pin. i 2 c interface is selected when ifs is unconnected, 3-wire interface is selected when ifs is connected to vss. 6c ei chip enable for 3-wire interface not used for i 2 c interface 7 sda/i/o i/o serial data input/output for i 2 c and 3-wire interfaces 8 scl/sclk i/o serial clock input for i 2 c and 3-wire interfaces 9 irq/fout o interrupt/frequency output, this pin is open drain output 10 vdd positive power supply HT1382 i 2 c/3-wire real time clock rev. 1.20 3 march 8, 2011

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approximate internal connections absolute maximum ratings supply voltage ...............................................................................................v ss 0.3v to v ss +6.0v input voltage .................................................................................................v ss 0.3v to v dd +0.3v storage temperature ................................................................................................. 50 cto125 c operating temperature................................................................................................ 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. rev. 1.20 4 march 8, 2011 HT1382 i 2 c/3-wire real time clock

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d.c. characteristics ta = 40c~85c symbol parameter test conditions min. typ. max. unit v dd conditions v dd supply voltage 2.7 5.5 v v bat battery supply voltage 2.0 5.5 v i stb standby current v bat =3v, ch=1 0.1 a i bat battery supply current v bat =3v, ch=0 1.2 a i dd1 supply current (low power mode) 3v scl/sclk=0hz, lpm=1 15 a 5v 30 a i dd2 supply current 3v scl/sclk=0hz, lpm=0 100 a 5v 150 a i dd3 supply current with i 2 c active 3v scl=400khz 150 a 5v 300 a i dd4 supply current with 3-wire active 3v sclk=1mhz 200 a 5v sclk=2mhz 500 a v ih h input voltage 0.7v dd v v il l input voltage 0.3v dd v v oh i/o high level output voltage 3v i oh1 = 1.5ma 2.7 v 5v i oh1 = 3.0ma 4.5 v v ol1 i/o, scl and sda low level output voltage 3v i ol1 = 3.0ma 0 0.4 v 5v i ol1 = 6.0ma 0 0.4 v v ol2 irq low level output voltage 3v i ol2 = 1.5ma 0 0.4 v 5v i ol2 = 3.0ma 0 0.4 v v comp v bat mode compared voltage 2.40 2.55 2.70 v hysteresis 25 mv v bathys v bat hysteresis 40 mv a.c. characteristics v dd =2.7v~5.5v, ta= 40c~85c power-down timing symbol parameter test conditions min. typ. max. unit v dd conditions t fsr vdd falling slew rate 10 v/ms note: in order to ensure proper timekeeping, the t fsr specification must be followed. HT1382 i 2 c/3-wire real time clock rev. 1.20 5 march 8, 2011
i 2 c interface symbol parameter remark min. typ. max. unit f scl clock frequency 400 khz t high clock high time 600 ns t low clock low time 1300 ns t r sda and scl rise time note 300 ns t f sda and scl fall time note 300 ns t hd:sta start condition hold time after this period, the first clock pulse is generated. 600 ns t su:sta start condition setup time only relevant for repeated start condition. 600 ns t hd:dat data input hold time 0 ns t su:dat data input setup time 100 ns t su:sto stop condition setup time 600 ns t aa output valid from clock 900 ns t buf bus free time time in which the bus must be free before a new transmission can start 1300 ns t sp input filter time constant (sda and scl pins) noise suppression time 50 ns note: these parameters are periodically sampled but not 100% tested 3-wire interface ta = 40c~85c symbol parameter test conditions min. typ. max. unit v dd conditions f sclk serial clock 3v 1 mhz 5v 2 mhz t dc data to clock setup 3v 100 ns 5v 50 ns t cdh clock to data hold 3v 140 ns 5v 70 ns t cdd clock to data delay 3v 400 ns 5v 200 ns t cl clock low time 3v 500 ns 5v 250 ns t ch clock high time 3v 500 ns 5v 250 ns t r clock rise and fall time 3v 1000 ns t f 5v 500 ns rev. 1.20 6 march 8, 2011 HT1382 i 2 c/3-wire real time clock
symbol parameter test conditions min. typ. max. unit v dd conditions t cc reset to clock setup 3v 2 s 5v 1 s t cch clock to reset hold 3v 120 ns 5v 60 ns t cwh reset inactive time 3v 2 s 5v 1 s t cdz reset to i/o high impedance 3v 140 ns 5v 70 ns timing diagrams power-down timing i 2 c interface HT1382 i 2 c/3-wire real time clock rev. 1.20 7 march 8, 2011 sda scl t f t hd:sda t low t r t hd:dat t su:dat t high t su:sta t hd:sta s sr t sp t su:sto p t buf s t aa sda out
3-wire interface read data transfer write data transfer rev. 1.20 8 march 8, 2011 HT1382 i 2 c/3-wire real time clock
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functional description the HT1382 is a low power real time clock device which provides full date and time functions. communication with the device is provided through two integral serial interfaces, i 2 c or 3-wire. the device version selects the type of interface. the clock and calendar information is generated in bcd format and also has alarm features. the calendar is accurate until the year 2099, with automatic leap year correction. basic timing is provided using an external 32768hz crystal, for which the device includes load capacitances of 12.5pf. an oscillator compensation function is provided to compensate for crystal oscillator temperatures. with fully integrated power control circuitry which can detect power failures, the device can automatically switch to a reserve battery supply when a power failure occurs. power control function the internal battery switchover circuit continually monitors the main power supply on the vdd pin and automatically switches to the backup battery supply when a power failure condition is detected. in the battery backup mode, the interface is disabled to minimise power consumption. the interface inputs will not be recognized which prevents extraneous data being written to the device. the interface outputs are high-impedance. all rtc function are operational when the device is in the battery backup mode. normal mode (v dd ) to battery backup mode (v bat ) to switch from the v dd to v bat mode , both of the following conditions must be valid: v dd v bat +v bathys or v dd >v comp +v comphys the power control situation is illustrated graphically below: low power mode in normal mode, the HT1382 switched into battery backup mode when the v dd power is lost. this will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. another mode, called low power mode, is available to allow direct switching from v dd to v bat without requiring v dd to drop below v comp . the power switchover circuit is disabled and less power is used while operating from v dd . low power mode is activated via the lpm bit. low power mode is useful when v dd is normally higher than v bat . the device will switch from v dd to v bat when v dd drops below v bat , with about 40mvof hysteresis to prevent any switchback of v dd after switchover. in a system with v dd =5v and v bat =3v, low power mode can be used. however, it is not recommended to use low power mode in v dd =3.3v 10%, v bat
3v. HT1382 i 2 c/3-wire real time clock rev. 1.20 9 march 8, 2011 battery backup mode v dd v comp v bat 2.55v 2.00v v bat -v bathys v bat +v bathys note: battery switchover when v bat clock compensation the device includes a digital trimming method for clock error correction due to temperature variations of the crystal oscillator. this can be implemented as manufacturing calibration or user active calibration. the crystal accuracy to temperature characteristic is similar to that shown in the diagram. the digital trimming register, dt, is used for clock compensation. correction is performed once every 10 seconds or 30 seconds. the minimum resolution is 3.052ppm or 1.017ppm and the device has a correction in the range of 192.276ppm or 64.071ppm. set fo3~fo0= 1010 , the fout pin will have 1hz clock pulse output. measure the fout frequency using a high-accuracy frequency counter with 7 or more digits. the correction value is calculated using the formula shown below. correction value = integral value ( 1hz - (measured value) minimum resolution (3.052p pm or 1.014ppm) ) when clock compensation is used, set fo3~fo0= 1010 , and the fout pin will have 1hz clock pulse output. the cycle changes once in 10 seconds or in 30 seconds as shown below. in the diagram a denotes a non-correctional cycle, and b denotes a correctional cycle. measure a and b using a high-accuracy frequency counter of 7 or more digits. calculate the average frequency based on the measured result. for dts = 0, the average period = (a 9+b) 10 for dts = 1, the average period = (a 29+b) 30 rev. 1.20 10 march 8, 2011 HT1382 i 2 c/3-wire real time clock
register description the device includes 16 registers which are used to control functions such as the rtc, status, alarm, frequency output etc. there are also five bytes of eeprom which contain the clock compensation settings and stored user data. the rtc and alarm register data is stored in bcd format, while other data is stored in binary format. the register map shows the address definitions for the i 2 c interface. the command byte and r/w bit are used for the 3-wire interface. address register definition register name range data default bit r/w command byte d7 d6 d5 d4 d3 d2 d1 d0 00h ch 10 sec sec seconds 00~59 80h w r 10000000 10000001 01h 0 10 min min minutes 00~59 00h w r 10000010 10000011 02h 12/ 24 0 0 ap 10 hr hr hour hours 01~12 00~23 12h w r 10000100 10000101 03h 0 0 10 date date date 01~31 01h w r 10000110 10000111 04h 0 0 0 10m month month 01~12 01h w r 10001000 10001001 05h 0 0 0 0 0 day day 01~07 01h w r 10001010 10001011 06h 10 year year year 00~99 00h w r 10001100 10001101 07h wp 0 0 0 0 0 0 0 st 80h w r 10001110 10001111 08h are 0 0 ewe eb ai be 0 st 00h w r 10010000 10010001 09h ime ae lpm oeobm fo3 fo2 fo1 fo0 int 00h w r 10010010 10010011 0ah secen al. 10sec al. sec seconds alarm 00~59 00h w r 10010100 10010101 0bh minen al. 10min al. min minutes alarm 00~59 00h w r 10010110 10010111 0ch hren 0 al. 10hr al. hour hours alarm 01~12 00~23 00h w r 10011000 10011001 0dh dten 0 al. 10dt al. date date alarm 01~31 00h w r 10011010 10011011 0eh moen 0 0 al. 10m al. month month alarm 01~12 00h w r 10011100 10011101 0fh dayen 0 0 0 0 al. day day alarm 01~07 00h w r 10011110 10011111 eeprom data 10h dts dt6 dt5 dt4 dt3 dt2 dt1 dt0 dt w r 10100000 10100001 11h eeprom user data usr w r 10100010 10100011 12h eeprom user data usr w r 10100100 10100101 13h eeprom user data usr w r 10100110 10100111 14h eeprom user data usr w r 10101000 10101001 HT1382 i 2 c/3-wire real time clock rev. 1.20 11 march 8, 2011
real time clock register the rtc register stores the year, day, month, date, hours, minutes and, second data in bcd format. 12/24 hour mode bit d7 of the hour register is defined as the 12-hour or 24-hours mode select bit. if the bit is 1 , the rtc uses a 24-hour format. if 0 , the rtc uses a 12-hour format. the default value is 0 . am/pm mode there are two function for the d5 bit in the hour register which is determined by the d7 bit. in the 12-hour mode the bit is used for am/pm selection. when d5 is 1 , it will be pm, otherwise it will be am. in the 24-hour mode, the bit is used to set the second 10-hour bit(20~23 hours). leap years leap years add an extra day for february 29 and are defined as those years that are divisible by 4. the device will provide automatic correction for leap years until year 2099. clock halt bit ch this bit enables/disables the oscillator. the ch bit is set high to disable the oscillator and cleared to zero is enable it. the default value is define as 1 . write protect bit wp the wp bit is set high to prevent data writes and cleared to zero to allow data to be written. the default value is define as 1 . battery enable bit be when the device enters the battery backup mode, the be bit is set to 1 . this bit can be cleared to 0 either manually by the user or automatically reset by the are pin. only a 0 an be written to this bit, not a 1 . alarm interrupt bit ai when the rtc register values match the alarm register values, the ai bit will be set to 1 . this bit can be reset to 0 either manually by the user or automatically reset by the are pin. only a 0 an be written to this bit, not a 1 . the ai bit will be set by an alarm occurring during a read operation ad will remain set until after the read operation is complete. auto reset enable bit are this bit enables/disables the automatic reset of the be and ai status bits only. when are is set to 1 , be and ai will be reset to 0 after reading these registers. when are is cleared to 0 , the user must manually reset the be and ai bits. eeprom write enable bit ewe when ewe is cleared to 0 , the eeprom is read only, and the user can not write data to the eeprom. when ewe is set to 1 , the user can write data to the eeprom. before writing data to the eeprom, this bit must be set to 1 . rev. 1.20 12 march 8, 2011 HT1382 i 2 c/3-wire real time clock
eeprom busy status bit eb this bit is set to 1 when a write operation to the eeprom has not completed. when this bit is set to 1 , reading data from the eeprom or writing data to the eeprom is invalid. after an eeprom write has finished, this bit will be cleared to 0 and the user can read data from the eeprom or write data to the eeprom. output enable on battery mode bit oeobm this bit enables/disables the irq /fout pin in the battery mode. when the oeobm bit is set to 1 , the irq /fout pin is disabled in the battery mode and the frequency output and alarm function are disabled. when the oeobm bit is cleared to 0 , the irq /fout pin is enabled in the battery mode. low power mode bit lpm this bit enables/disables the low power mode. when the lpm bit is cleared to 0 , the device will be in the normal mode and will use the v bat supply when v dd HT1382 i 2 c/3-wire real time clock rev. 1.20 13 march 8, 2011
alarm enable bit ae this bit enables/disables the alarm function. when the ae bit is set to 1 , the alarm function is enabled. when the ae bit is cleared to 0 , the alarm function is disabled. digital trimming setting bits dts this bit sets the digital trimming resolution and adjustment time. the user must detect the status of the eb bit before reading data or writing data. if the eb bit is 0 , it is valid to read data or write data. if the eb bit is 1 , it is invalid to read data or write data. dts=0 dts=1 adjustment time every 10 seconds every 30 seconds minimum resolution 3.052ppm 1.017ppm correction range -192.276ppm to +192.276ppm -64.071ppm to + 64.071ppm digital trimming bits dt6~dt0 this digital trimming bit, dt6, is the sign bit. a 0 indicates positive calibration and a 1 indicates negative calibration. dt5~dt0 are the calibration values and the adjustable range is -63 ~ +63. if dts is cleared to 0 , the correction range is -192.276ppm to +192.276ppm and if dts is set to 1 , the correction range is -64.071ppm to +64.071ppm. the user must detect the status of eb bit before reading data or writing data. if the eb bit is 0 , it is valid to read data or write data. if the eb bit is 1 , it is invalid to read data or write data. dt6 dt5 dt4 dt3 dt2 dt1 dt0 value correction value (ppm) dts=0 dts=1 0111111+63 +192.276 +64.071 0111110+62 +189.224 +63.054 0111101+61 +186.172 +62.037 0111100+6 +183.120 +61.020 : : : : : : 00100011+3 +9.156 +3.051 0000010+2 +6.104 +2.034 0000001+1 +3.052 +1.017 00000000 0 0 10000000 0 0 1000001-1 -3.052 -1.07 1000010-2 -6.104 -2.034 1000011-3 -9.156 -3.051 : : : : : : 1111100-60 -183.120 -61.020 1111101-61 -186.172 -62.037 1111110-62 -189.224 -63.054 1111111-63 -192.276 -64.071 rev. 1.20 14 march 8, 2011 HT1382 i 2 c/3-wire real time clock
interrupt mode enable bit ime this bit enables/disables the interrupt mode of the alarm function. when the ime bit is set to 1 , the interrupt mode is enabled and when the ime bit is cleared to 0 , the interrupt mode is disabled and the alarm operates in single mode. alarm register the addresses of alarm registers are 0bh to 10h. the data is stored in the bcd format. the msb of each alarm register is an enable bit. (enable= 1 ). these enable bits specify which alarm registers are used to make the comparison between the alarm registers and the rtc registers. there is no alarm byte for year. when a compare match condition exists, the ai bit is set to 1 , and the irq pin is activated. to clear an alarm, the ai bit must be cleared to 0 . if the are bit is set to 1 , the ai bit will automatically be cleared when the status register is read. there are two alarm operation modes: single mode and interrupt mode. single mode: set the ae bit to 1 , the ime bit to 0 , and disable the frequency output. when the rtc register values match the alarm registers values, the ai bit will be set to 1 and the alarm condition activates the irq pin. the irq pin will remain low until the ai bit is cleared to 0 . interrupt mode: set the ae bit to 1 , the ime bit to 1 , and disable the frequency output. when the rtc registers values match the alarm registers values, the irq pin will be pulled low for 250ms and the ai bit will be set to 1 . this mode allows for a repetitive or recurring alarm function. when the alarm is set, the device will continue to activate an alarm for each match of the alarm and the present time. for example, if only the seconds are set, it will activate an alarm every minute, if only the minutes are set, it will activate an alarm every hour. eeprom user data the HT1382 provides 4 bytes eeprom for user. the eeprom will continue to operate in battery backup mode. however, it should be noted that the i 2 c/3-wire interface is disabled in battery backup mode. user must detect the status of eb bit before reading data or writing data. if the eb bit is 0 ,itis valid to read data or write data. if the eb bit is 1 , it is invalid to read data or write data. HT1382 i 2 c/3-wire real time clock rev. 1.20 15 march 8, 2011
i 2 c serial interface the HT1382 includes an i 2 c serial interface. the i 2 c bus is used for bidirectional, two-line communication between multiple i 2 c devices. the two lines of the interface are the serial data line (sda) and the serial clock line (scl).both lines are connected to the positive supply via a pull-up resistor externally. when the bus is free, both lines will be high. the output stages of the devices connected to the bus must have open-drain or open-collector output types to implement the wired-and function necessary for connection. data transfer is initiated only when the bus is not busy. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions a high to low transition on the sda line while scl is high defines a start condition. a low to high transition on the sda line while scl is high defines a stop condition. start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus stays busy if a repeated start(sr) is generated instead of a stop condition. in this respect, a start(s) and repeated start(sr) conditions are functionally identical. byte format every byte put on the sda line must be 8-bits long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most significant bit (msb) first. rev. 1.20 16 march 8, 2011 HT1382 i 2 c/3-wire real time clock sda scl data line stable; data valid change of data allowed p s sda scl sda scl start condition sto p condition s or sr p or sr sda scl 12 78 9 ack 12 3-8 9 ack p sr
acknowledge each bytes of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level placed on the bus by the receiver. the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge (ack) after the reception of each byte. the acknowledging device must first pull down the sda line during the acknowledge clock pulse so that it remains low during the high period of this clock pulse. a master receiver must signal an end of data to the slave by generating a not-acknowledge (nack) bit on the last byte that has been clocked out of the slave. in this case, the master receiver must leave the data line high during the 9th pulse to not acknowledge. the master will generate a stop or repeated start condition. device addressing the slave address byte is the first byte received following the start condition from the master device. the first seven bits of the first byte make up the slave address. the eighth bit defines a read or write operation to be performed. when this r/w bit is 1 , then a read operation is selected. a 0 selects a write operation. the device address bits are 1101000 . when an address byte is sent, the device compares the first seven bits after the start condition. if they match, the device outputs an acknowledge on the sda line. write operation byte write operation a byte write operation requires a start condition, a slave address with r/ bit, a valid register address, the required data and a stop condition. after each of the three byte transfers, the device responds with an ack. page write operation following a start condition and slave address, a r/ bit is placed on the bus which indicates to the addressed device that a register address will follow which is to be written to the address pointer. the data to be written to the memory follows next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. after reaching memory location 0fh, the pointer will be reset to 00h. byte write sequence HT1382 i 2 c/3-wire real time clock rev. 1.20 17 march 8, 2011 s 12 78 9 clk pulse for acknowledgement data output by transmitter data output by receiver scl from master acknowledge not acknowledge start condition 110 1 0 0 0 r/ w msb lsb the first byte after the start. 11 0 100 0 0 s ack p slave address write register address(an) data(n) ack ack
page write sequence read operation in this mode, the master reads the device data after setting the slave address. following the r/w bit (= 0 ) and the acknowledge bit, the register address (an) is written to the address w pointer. next the start condition and slave address are repeated followed by the r/w bit (= 1 ). the data which was addressed is then transmitted. the address pointer is only incremented on reception of an acknowledge clock. the device will then place the data at address an+1 on the bus. the master reads and acknowledges the new byte and the address pointer is incremented to an+2 . after reaching the memory location 0fh, the pointer will be reset to 00h. this cycle of reading consecutive addresses will continue until the master sends a stop condition. read sequence 3-wire serial interface the device also support a 3-wire serial interface. the ce pin is used to identify the transmitted data. the transmission is controlled by the active high signal ce. each data transfer is a byte, with the lsb sent first. the first byte transmitted is the command byte. command byte for each data transfer, a command byte is initiated to specify which register is accessed. this is to determine whether a read or write cycle is operational and whether a single byte or burst mode transfer is to occur. r/w signal the lsb of the command byte determines whether the data in the register is to be read or be written to. if it is 0 then this means that it is a write cycle. if it is 1 then this means that it is a read cycle. burst mode when the command byte is 10 111110 or 10111111, the device is configured in the burst mode. in this mode, the address of registers from 00h to 0fh can be written or read in series, starting with bit 0 of register address 0. rev. 1.20 18 march 8, 2011 HT1382 i 2 c/3-wire real time clock 11 0 100 0 1 s read data(n) ack data(n+1) data(n+x) p 11 0 100 0 0 s ack slave address write register address(an) p ack slave address ack ack ack ack 11 0 100 0 0 s data(n+1) data(n+x) p slave address write register address(an) data(n) ack ack ack ack ack ack
data input and data out in writing a data byte, r/w is cleared to 0 in the command byte and is then followed by the corresponding data register address on the rising edge of the next eight sclk. additional sclk cycles are ignored. data inputs are entered starting with bit 0. in reading data from the register, the r/w is set to 1 in the command byte. the data bits are output on the falling edge of the next eight sclk cycles. note that the first data bit to be transmitted on the first falling edge after the last bit of the read command byte is written. additional sclk cycles re-transmits the data bytes as long as ce remains at high level. data outputs are read starting with bit 0. single byte transfer burst mode transfer HT1382 i 2 c/3-wire real time clock rev. 1.20 19 march 8, 2011 2 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # & ' ' ( ) * # + % ,
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application circuits i 2 c serial interface 3-wire serial interface rev. 1.20 20 march 8, 2011 HT1382 i 2 c/3-wire real time clock

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package information 8-pin dip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.355 0.375 b 0.240 0.260 c 0.125 0.135 d 0.125 0.145 e 0.016 0.020 f 0.050 0.070 g 0.100 h 0.295 0.315 i 0.375 symbol dimensions in mm min. nom. max. a 9.02 9.53 b 6.10 6.60 c 3.18 3.43 d 3.18 3.68 e 0.41 0.51 f 1.27 1.78 g 2.54 h 7.49 8.00 i 9.53 HT1382 i 2 c/3-wire real time clock rev. 1.20 21 march 8, 2011

8-pin sop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.012 0.020 c 0.188 0.197 d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010 08 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.30 0.51 c 4.78 5.00 d 1.75 e 1.27 f 0.10 0.25 g 0.41 1.27 h 0.18 0.25 08 rev. 1.20 22 march 8, 2011 HT1382 i 2 c/3-wire real time clock

8-pin tssop outline dimensions symbol dimensions in inch min. nom. max. a 0.041 0.047 a1 0.002 0.006 a2 0.031 0.041 b 0.010 c 0.004 0.006 d 0.114 0.122 e 0.244 0.260 e1 0.169 0.177 e 0.026 l 0.020 0.028 l1 0.035 0.043 y 0.004 08 symbol dimensions in mm min. nom. max. a 1.05 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.25 c 0.11 0.15 d 2.90 3.10 e 6.20 6.60 e1 4.30 4.50 e 0.65 l 0.50 0.70 l1 0.90 1.10 y 0.10 08 HT1382 i 2 c/3-wire real time clock rev. 1.20 23 march 8, 2011

8-pin msop outline dimensions mo-187 symbol dimensions in inch min. nom. max. a 0.043 a1 0.000 0.006 a2 0.030 0.037 b 0.009 0.013 c 0.003 0.009 d 0.012 e 0.193 e1 0.118 e 0.026 l 0.016 0.031 l1 0.037 y 0.004 08 symbol dimensions in mm min. nom. max. a 1.10 a1 0.00 0.15 a2 0.75 0.95 b 0.22 0.33 c 0.08 0.23 d 3.00 e 4.90 e1 3.00 e 0.65 l 0.40 0.80 l1 0.95 y 0.10 08 rev. 1.20 24 march 8, 2011 HT1382 i 2 c/3-wire real time clock

10-pin msop outline dimensions symbol dimensions in inch min. nom. max. a 0.043 a1 0.000 0.006 a2 0.030 0.033 0.037 b 0.007 0.011 c 0.010 d 0.012 e 0.193 e1 0.118 e 0.020 l 0.016 0.024 0.031 l1 0.037 08 symbol dimensions in mm min. nom. max. a 1.10 a1 0.00 0.15 a2 0.75 0.85 0.95 b 0.17 0.27 c 0.25 d 3.00 e 4.90 e1 3.00 e 0.50 l 0.40 0.60 0.80 l1 0.95 08 HT1382 i 2 c/3-wire real time clock rev. 1.20 25 march 8, 2011

reel dimensions sop 8n symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 12.8 +0.3/-0.2 t2 reel thickness 18.20.2 tssop 8l symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 12.8 +0.3/-0.2 t2 reel thickness 18.20.2 rev. 1.20 26 march 8, 2011 HT1382 i 2 c/3-wire real time clock

carrier tape dimensions sop 8n symbol description dimensions in mm w carrier tape width 12.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 5.50.1 d perforation diameter 1.550.1 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.40.1 b0 cavity width 5.20.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 9.30.1 HT1382 i 2 c/3-wire real time clock rev. 1.20 27 march 8, 2011

! " # $ % & $ ' # ( ) $ ) * ! + , - + . - / $ , - . % $ ! * . ) ! + / $ 0 / ( * - . -
tssop 8l symbol description dimensions in mm w carrier tape width 12.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 5.50.5 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.5 +0.1/-0.0 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 7.00.1 b0 cavity width 3.60.1 k0 cavity depth 1.60.1 t carrier tape thickness 0.3000.013 c cover tape width 9.30.1 rev. 1.20 28 march 8, 2011 HT1382 i 2 c/3-wire real time clock
HT1382 i 2 c/3-wire real time clock rev. 1.20 29 march 8, 2011 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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